Key Selection Information
| Selection Parameter | Confirmed Information |
|---|---|
| Function | 8-bit parallel-load, serial-output shift register |
| Parallel Inputs | A–H loaded when SH/LD is low |
| Serial | SER input allows cascading |
| Outputs | QH and complementary output |
| Clock Control | CLK plus CLK INH gated clock function |
| Supply | 2 V to 6 V |
| Use | Parallel-to-serial input expansion |
| Exact Package / Packing | TSSOP (PW), 16 pins; large tape and reel |
Product Overview
SN74HC165PWR performs the opposite direction from HC164/595: it captures eight parallel logic inputs and shifts them to a serial output. It is useful for expanding switches, status lines and digital sensors into one MCU input.
The active-low SH/LD input captures all eight pins at one instant before shifting, preserving a coherent snapshot rather than reading lines sequentially. Multiple devices can be cascaded through SER/QH to collect wider input words.
Clock inhibit provides explicit control over shifting and can prevent spurious clocks from altering the captured sequence during bus sharing or firmware setup.
For related devices, see HKEQGOO’s Shift Registers category.
Technical Specifications
| Parameter | Verified Information |
|---|---|
| Manufacturer | Texas Instruments |
| Exact MPN | SN74HC165PWR |
| Function | 8-bit parallel-load, serial-output shift register |
| Parallel Inputs | A–H loaded when SH/LD is low |
| Serial | SER input allows cascading |
| Outputs | QH and complementary output |
| Clock Control | CLK plus CLK INH gated clock function |
| Supply | 2 V to 6 V |
| Use | Parallel-to-serial input expansion |
| Exact Package / Packing | TSSOP (PW), 16 pins; large tape and reel |
| Manufacturer Status | Active / Production |
| Part Marking | HC165 |
Functional Highlights
Parallel load creates a simultaneous input snapshot
This matters when several status bits may change while the MCU is reading them; a latched snapshot avoids a word made from different moments in time.
Cascading scales input count with few MCU pins
One load signal, one clock and one serial data line can read multiple chained devices, at the cost of longer scan time.
Design Considerations
- Meet SH/LD setup/hold around the desired snapshot instant.
- Calculate total scan time for chained devices against how quickly input states can change.
- Use clock inhibit/default levels to prevent accidental shifts from shared/noisy clocks.
Product Status and Exact Order Code
Manufacturer status: Active / Production
Texas Instruments lists SN74HC165PWR as Active / Production; TSSOP (PW), 16 pins; large tape-and-reel; −40°C to +125°C family orderable range.
Related Engineering Resources
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