Key Selection Information
| Selection Parameter | Confirmed Information |
|---|---|
| Function | 8-bit serial-in, parallel-out shift register |
| Serial Input | AND-gated A/B serial inputs |
| Clear | Asynchronous direct clear |
| Clock | Positive-edge shift clock |
| Supply | 2 V to 6 V |
| Output | 8 continuously visible parallel outputs; no storage latch |
| Drive | ±4 mA at 5 V stated feature |
| Exact Package / Packing | SOIC (D), 14 pins; large tape and reel |
Product Overview
SN74HC164DR converts serial data to eight parallel outputs with a very simple shift-register architecture. Because there is no separate output/storage latch, every clocked bit movement is visible immediately at QA–QH.
That behavior is ideal for applications where shifting outputs are acceptable or desired, but it can cause visible intermediate states on LEDs, relays or control lines. SN74HC595/594 should be considered when the system needs to shift data invisibly and then update outputs as a group.
DR selects the larger SOIC-14 reel format; its electrical behavior is the same HC164 core as PWR, while package area and assembly/rework are different.
For related devices, see HKEQGOO’s Shift Registers category.
Technical Specifications
| Parameter | Verified Information |
|---|---|
| Manufacturer | Texas Instruments |
| Exact MPN | SN74HC164DR |
| Function | 8-bit serial-in, parallel-out shift register |
| Serial Input | AND-gated A/B serial inputs |
| Clear | Asynchronous direct clear |
| Clock | Positive-edge shift clock |
| Supply | 2 V to 6 V |
| Output | 8 continuously visible parallel outputs; no storage latch |
| Drive | ±4 mA at 5 V stated feature |
| Exact Package / Packing | SOIC (D), 14 pins; large tape and reel |
| Manufacturer Status | Active / Production |
| Part Marking | HC164 |
Functional Highlights
No output latch is the defining behavioral constraint
The parallel outputs change on each shift clock. Firmware cannot preload a new 8-bit word without exposing the intermediate bit sequence.
AND-gated A/B inputs can act as a serial-data enable
Holding either serial input low blocks a high from entering the first stage, allowing simple gating without an extra logic gate.
Design Considerations
- Do not drive glitch-sensitive loads directly if intermediate shift states are unacceptable.
- Use CLR for a deterministic asynchronous all-zero state and verify its reset timing.
- Choose SOIC DR vs TSSOP PWR from board/assembly needs, not an assumed electrical-grade difference.
Product Status and Exact Order Code
Manufacturer status: Active / Production
Texas Instruments lists SN74HC164DR as Active / Production; SOIC (D), 14 pins; large tape-and-reel; −40°C to +125°C family orderable range.
Related Engineering Resources
Quality & Verification Support
Third-party inspection or testing can be arranged according to customer requirements. Testing fees are borne by the buyer. Additional verification requirements can be discussed before shipment. After an order is placed, physical product, label, packaging, and Date Code photos may be provided where appropriate.
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