Key Selection Information
| Selection Parameter | Confirmed Information |
|---|---|
| Package | TSSOP-20 |
| Supply voltage | 2V~3.6V |
| CPU Core | Arm Cortex-M0+ |
| Maximum CPU speed | 64MHz |
| Program memory | 32KB |
| Operating Temperature | -40℃~+85℃ |
| Number of I/O | 17 |
Compact STM32G0 in a TSSOP-20 orderable
STM32G030F6P6TR is a 64 MHz Arm Cortex-M0+ MCU with 32 KB of Flash and 8 KB of SRAM in the STM32G0 value line. The exact P6TR orderable uses a TSSOP-20 package and tape-and-reel packing, which makes package footprint and assembly format part of the procurement identity.
The family provides two USARTs, two SPI interfaces with one multiplexed for I2S, I2C communication and a 12-bit ADC. In this 20-pin version, the useful question is not the maximum family peripheral list but whether the required signals fit the restricted package pin map.
Technical Specifications
| Parameter | Value |
|---|---|
| Package | TSSOP-20 |
| Supply voltage | 2V~3.6V |
| CPU Core | Arm Cortex-M0+ |
| Maximum CPU speed | 64MHz |
| Program memory | 32KB |
| Operating Temperature | -40℃~+85℃ |
| Number of I/O | 17 |
| ADC (Bit) | 12bit |
| Program Memory Type | FLASH |
| Core Size | 32 Bit |
| Oscillator Type | Built-in+External |
P6TR is a package-and-packing decision
The F6 code fixes the 32 KB Flash density, P6 identifies the TSSOP-20 industrial package, and TR identifies tape-and-reel packing. That makes this SKU materially different in PCB footprint and assembly logistics from LQFP STM32G030 variants even when the CPU and memory are similar.
Small-package resource budgeting
Start the design from the TSSOP-20 pinout, then allocate debug, clock, ADC and serial functions before counting spare GPIO. Two USARTs and two SPI blocks exist at family level, but alternate-function sharing means interface concurrency must be checked against the exact 20-pin mapping rather than assumed from the peripheral list.
Where this orderable makes sense
This device is a good fit for compact, cost-sensitive controllers where 32 KB of program storage, modest serial connectivity and a small TSSOP footprint are more important than a large I/O count. Projects likely to add more interfaces or firmware features should evaluate a larger STM32G0 package before layout.
Keep pin and firmware margin visible
Use the 2.0 V to 3.6 V supply range in the power-domain review and preserve Flash margin beyond the first firmware build. Because the exact orderable is tape-and-reel, it also fits automated assembly workflows differently from non-TR packing variants; that is a procurement distinction, not an electrical-performance difference.
Related Engineering Resources
- STM32G030F6P6TR Datasheet (PDF) — HKEQGOO-hosted technical copy for engineering review.
- STMicroelectronics product page — official manufacturer product, lifecycle and ordering resource.
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