Key Selection Information
| Selection Parameter | Confirmed Information |
|---|---|
| Channels | 2 bidirectional lines for SDA/SCL |
| Interfaces | I²C and SMBus; also suitable for similar open-drain signals |
| VREF1 | 1.2 V to 3.3 V class |
| VREF2 | 1.8 V to 5.5 V class |
| Direction | No direction pin |
| On-Resistance | 3.5 Ω stated low ON resistance |
| Enable | High-impedance isolation when EN is low |
| Exact Package / Packing | SSOP (DCT), 8 pins; 3000-piece large reel; −40°C to +85°C; marking 7BD variants |
Product Overview
PCA9306DCTR is a classic two-line pass-FET translator focused on I²C/SMBus domain bridging. It allows the pull-ups on each side to establish different bus-high voltages while preserving open-drain wired-AND behavior.
Its low propagation delay is primarily the pass-path delay; real bus speed is still governed by pull-up resistance and capacitance on each side. It is therefore appropriate to think of PCA9306 as a voltage-domain bridge, not an active edge accelerator.
Compared with newer TCA39306, PCA9306 has a higher minimum low-side reference voltage and older temperature/speed positioning. The exact DCTR option is an SSOP-8 3000-piece reel.
For related devices, see HKEQGOO’s Translators, Level Shifters category.
Technical Specifications
| Parameter | Verified Information |
|---|---|
| Manufacturer | Texas Instruments |
| Exact MPN | PCA9306DCTR |
| Channels | 2 bidirectional lines for SDA/SCL |
| Interfaces | I²C and SMBus; also suitable for similar open-drain signals |
| VREF1 | 1.2 V to 3.3 V class |
| VREF2 | 1.8 V to 5.5 V class |
| Direction | No direction pin |
| On-Resistance | 3.5 Ω stated low ON resistance |
| Enable | High-impedance isolation when EN is low |
| Exact Package / Packing | SSOP (DCT), 8 pins; 3000-piece large reel; −40°C to +85°C; marking 7BD variants |
| Manufacturer Status | Active / Production |
| Part Marking | 7BD family marking variants |
Functional Highlights
Open-drain semantics are preserved across domains
Multiple I²C controllers/slaves can still pull the shared line low without a direction state machine.
EN provides clean bus isolation
A downstream domain can be disconnected during power-off or fault recovery, leaving both sides high impedance.
Design Considerations
- Calculate pull-ups separately on each bus side.
- Do not use the pass translator to “fix” a bus whose capacitance already violates I²C rise-time limits.
- Check VREF1/VREF2 bias relationship during sequencing.
Product Status and Exact Order Code
Texas Instruments/source evidence identifies PCA9306DCTR as Active / Production; SSOP (DCT), 8 pins; 3000-piece large tape and reel; −40°C to +85°C.
Related Engineering Resources
Quality & Verification Support
Third-party inspection or testing can be arranged according to customer requirements. Testing fees are borne by the buyer. Additional verification requirements can be discussed before shipment. After an order is placed, physical product, label, packaging, and Date Code photos may be provided where appropriate.
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