Device Overview
Microchip Technology ENC28J60-I/SO integrates a 10BASE-T Ethernet MAC and PHY with an SPI host interface, allowing a microcontroller to add wired Ethernet without an external MAC/PHY pair.
Selection-Critical Data
| Parameter | Confirmed Data | Engineering Relevance |
|---|---|---|
| Ethernet function | Stand-alone 10BASE-T controller with integrated MAC and PHY | Defines the network function and PHY speed that the host design expects. |
| Ethernet speed | 10 Mbps | Sets the link-rate class and network compatibility. |
| Host interface | SPI | Must match the microcontroller peripheral and firmware interface. |
| Maximum SPI clock | 25 MHz | Sets the upper host-interface clock rate. |
| Packet buffer | 8 Kbyte dual-port TX/RX buffer | Provides packet-storage capacity between Ethernet traffic and host servicing. |
| Digital I/O voltage | 3.3 V | Must be compatible with the host logic domain. |
| Package | SOIC-28 | Defines footprint and orderable-package compatibility. |
Selection Note
For a replacement, Ethernet speed, SPI compatibility, packet-buffer architecture and package must be checked together; the 8 Kbyte buffer is a memory resource for packet handling, not a logic truth-table characteristic.
