Key Selection Information
| Selection Parameter | Confirmed Information |
|---|---|
| Function | 8-bit serial-in shift register with output storage register |
| Parallel outputs | 8, 3-state |
| Supply range | 2.0 V to 5.5 V |
| Logic family | AHC CMOS |
| Output drive | ±8 mA class |
| Maximum frequency | 170 MHz parametric value |
| Package | TSSOP16 / SOT403-1 |
| Product status | Active |
Product Overview
The 74AHC595PW,118 is Nexperia’s active TSSOP16 reel orderable for an 8-bit serial-in shift register with a separate storage register and 3-state parallel outputs. Separate shift and latch clocks allow new serial data to be loaded without disturbing the currently displayed parallel state until the storage register is updated.
A serial output enables multiple devices to be cascaded for wider output expansion. The output-enable input can place all parallel outputs in high impedance without clearing either register, which is useful during bus handover or system startup.

Technical Specifications
| Parameter | Confirmed Information |
|---|---|
| Shift-register width | 8 bit |
| Storage register | 8 bit |
| Supply voltage | 2.0 V to 5.5 V |
| Logic input levels | CMOS |
| Output drive | ±8 mA class |
| Propagation delay | 4.0 ns parametric reference |
| Maximum frequency | 170 MHz parametric reference |
| Parallel outputs | 3-state |
| Operating temperature | -40°C to +125°C |
| RθJA for PW package | Approximately 122 K/W |
| Package | TSSOP16 / SOT403-1 |
Design Considerations
Keep OE inactive/high while outputs must not drive the bus during power-up or data loading. This avoids contention while the shift and storage registers are being initialized.
The AHC version uses CMOS thresholds; the related AHCT595 uses TTL-compatible thresholds. Those variants are not interchangeable when the driving logic-high level is close to the input threshold.
Related Engineering Resources
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