Key Selection Information
| Selection Parameter | Confirmed Information |
|---|---|
| Function | IEEE 802.3af/at/bt PoE powered-device interface |
| Maximum PD class support | Up to 71.3 W PD operation |
| Current control | Configurable inrush and operating current limits |
| External power FET support | GATE1 driver for external MOSFET |
| Auxiliary-input support | AUX detector and GATE2 N-channel MOSFET driver |
| Detection | Integrated PoE detection resistor |
| Thermal protection | 150°C over-temperature protection |
| Packing suffix | -Z tape-and-reel ordering option |
Product Overview
The MP8020GQV-Z is the tape-and-reel orderable version of MPS’s MP8020 IEEE 802.3af/at/bt PoE powered-device interface. It handles the PD-side detection and power-entry functions while providing configurable current limiting and gate-drive support for external MOSFETs in higher-power designs.
Unlike a PoE controller with an integrated downstream DC/DC converter, the MP8020 is primarily the powered-device interface. Its power-good output is intended to enable the following converter, while GATE1, GATE2 and the auxiliary-input detector allow the power path to be adapted for higher load power or wall-adapter operation.
Technical Specifications
| Parameter | Confirmed Information |
|---|---|
| PoE standards | IEEE 802.3af / 802.3at / 802.3bt |
| Maximum PD operation | 71.3 W class support stated for MP8020 |
| Inrush current limit | Configurable |
| Normal operating current limit | Configurable |
| Detection resistor | Integrated |
| Maintain power signature | Automatic MPS support |
| External MOSFET drive | GATE1 |
| Adapter path drive | GATE2 N-channel MOSFET driver |
| Power-good output | Provided for downstream DC/DC enable |
| Over-temperature protection | 150°C |
| Package | QFN-18, 3 mm × 5 mm |
| Tape/reel quantity | 5,000 for MP8020GQV-Z manufacturer ordering table |
Design Considerations
The maximum PoE power class is not a guarantee that every implementation can deliver 71.3 W at the load. The external MOSFET, cable allocation, downstream converter, thermal design and IEEE class negotiation all have to support the intended power level.
For designs above the efficient range of the internal power path, use the GATE1 external-MOSFET architecture described by MPS. The downstream DC/DC stage remains a separate design responsibility and should not be sized from the PD-interface rating alone.
Related Engineering Resources
Quality & Verification Support
Third-party inspection or testing can be arranged according to customer requirements. Testing fees are borne by the buyer. Additional verification requirements can be discussed before shipment. After an order is placed, physical product, label, packaging, and Date Code photos may be provided where appropriate.
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