Device Overview
IESC1000 is a Qorvo Power Application Controller built around a 50 MHz ARM Cortex-M0 core. Unlike a simple gate-driver IC, it combines embedded control resources with analog acquisition, PWM generation, serial communications and configurable power-management functions in one TQFN-48 package.
The controller includes up to 32 kB of embedded Flash and 8 kB of SRAM. Its analog subsystem includes a 10-bit ADC with 1 µs conversion timing and dual auto-sampling sequencers, while the digital control resources include a 14-channel PWM engine plus SPI, I2C and UART interfaces.
Selection-Critical Architecture
| Parameter | Confirmed Information | Conditions / Notes |
|---|---|---|
| Device function | Power Application Controller | Exact manufacturer architecture |
| Processor core | ARM Cortex-M0 | 50 MHz core |
| Core clock | 50 MHz | |
| Embedded Flash | Up to 32 kB | |
| SRAM | 8 kB | |
| ADC | 10-bit / 1 µs | Dual auto-sampling sequencers |
| PWM engine | 14 channels | |
| Serial interfaces | SPI, I2C, UART | |
| Power-manager modes | Buck, SEPIC, AC/DC flyback | Configurable switching-supply controller |
| Package | TQFN-48, 6 x 6 mm | Exact variant |
Engineering Selection Notes
IESC1000 should be evaluated as a controller platform rather than as a single-function controller or driver IC. The 50 MHz Cortex-M0 core, Flash/SRAM resources, ADC and PWM engine determine how much control firmware and time-critical signal handling can remain inside the device.
Its configurable power-manager modes are another major differentiator. A design that depends on buck, SEPIC or AC/DC flyback control should compare those functions explicitly rather than assuming that another Cortex-M0 controller with similar memory is equivalent.
The 14-channel PWM engine and dual-sequencer ADC matter when multiple control waveforms must be generated while analog signals are sampled under firmware control. SPI, I2C and UART define the principal documented serial integration paths.
The 6 x 6 mm TQFN-48 package is an independent PCB-footprint and assembly constraint, so a functionally similar controller still requires package-level compatibility review.
