Key Selection Information
| Selection Parameter | Confirmed Information |
|---|---|
| Function | 8-bit serial-in / parallel-out shift register |
| Supply range | 2.0 V to 6.0 V |
| Clock | LOW-to-HIGH edge |
| Reset | Asynchronous active-low master reset |
| Output drive | ±5.2 mA class |
| Package | SO14 / SOT108-1 |
| Exact OPN state | RFS / released for sale |
Product Overview
The 74HC164D,653 is the Nexperia SO14 orderable of the 74HC164 8-bit serial-in, parallel-out shift register. It uses two gated serial inputs, a positive-edge clock and an asynchronous active-low master reset.
The two serial inputs can be combined logically, so applications using only one data source should tie the other input to the intended enabling level.
Technical Specifications
| Parameter | Confirmed Information |
|---|---|
| Register width | 8 bit |
| Supply voltage | 2.0–6.0 V |
| Clock edge | LOW-to-HIGH |
| Reset | Asynchronous active-low |
| Output drive | ±5.2 mA class |
| Maximum frequency | ≥27 MHz at 4.5 V over full temperature range |
| Typical frequency | 55 MHz at 25°C / 4.5 V |
| Typical tPD | 17 ns at 4.5 V |
| Input capacitance | 3.5 pF typical |
| Temperature range | -40°C to +125°C |
| Package | SO14 |
Design Considerations
MR should be held at a defined level during power-up to avoid unintended clearing. If one serial input is unused, tie it high or low according to the desired gating behavior.
Use HC logic thresholds, not HCT thresholds, when checking the driving source.
Related Engineering Resources
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Third-party inspection or testing can be arranged according to customer requirements. Testing fees are borne by the buyer. Additional verification requirements can be discussed before shipment. After an order is placed, physical product, label, packaging, and Date Code photos may be provided where appropriate.
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