Key Selection Information
| Selection Parameter | Confirmed Information |
|---|---|
| Function | 3-line to 8-line decoder/demultiplexer |
| Outputs | 8 mutually exclusive active-low outputs |
| Enable | Three enable inputs support cascading/data routing |
| Supply | 2 V to 6 V |
| Delay | 15 ns typical stated feature |
| Drive | ±4 mA at 5 V; up to 10 LSTTL loads |
| Power | 80 µA maximum ICC stated feature |
| Exact Package / Packing | TSSOP (PW), 16 pins; 2000-piece large tape and reel |
Product Overview
SN74HC138PWR converts a 3-bit binary address into one of eight active-low outputs and includes three enable inputs for cascading. It is commonly used for chip-select generation, address decoding and one-of-eight control.
The HC implementation operates from 2 V to 6 V and has much lower static supply current than LS-TTL logic. That makes it more suitable for modern CMOS systems than SN74LS138 when the existing design is not locked to 5 V TTL characteristics.
PWR is the TSSOP large-reel package, providing the same logical function as other HC138 packages in a smaller leaded footprint.
For related devices, see HKEQGOO’s Signal Switches, Multiplexers, Decoders category.
Technical Specifications
| Parameter | Verified Information |
|---|---|
| Manufacturer | Texas Instruments |
| Exact MPN | SN74HC138PWR |
| Function | 3-line to 8-line decoder/demultiplexer |
| Outputs | 8 mutually exclusive active-low outputs |
| Enable | Three enable inputs support cascading/data routing |
| Supply | 2 V to 6 V |
| Delay | 15 ns typical stated feature |
| Drive | ±4 mA at 5 V; up to 10 LSTTL loads |
| Power | 80 µA maximum ICC stated feature |
| Exact Package / Packing | TSSOP (PW), 16 pins; 2000-piece large tape and reel |
| Manufacturer Status | Active / Production |
| Part Marking | HC138 |
Functional Highlights
Enable pins simplify larger decoders without extra gates
Multiple HC138 devices can be cascaded using the active-high/active-low enable combination, reducing external decode logic.
Active-low outputs must match the controlled peripheral polarity
The selected output goes low while the others remain high. A peripheral requiring active-high chip select needs inversion or a different decoder function.
Design Considerations
- Verify VIH/VIL against the source logic at the chosen VCC rather than relying only on nominal 5 V compatibility.
- Include propagation delay in address/chip-select timing around fast memory/peripheral buses.
- Default the enable network so no unintended chip select occurs during host reset.
Product Status and Exact Order Code
Manufacturer status: Active / Production
Texas Instruments lists SN74HC138PWR as Active / Production; TSSOP (PW), 16 pins; large tape-and-reel; −40°C to +85°C orderable range.
Related Engineering Resources
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Third-party inspection or testing can be arranged according to customer requirements. Testing fees are borne by the buyer. Additional verification requirements can be discussed before shipment. After an order is placed, physical product, label, packaging, and Date Code photos may be provided where appropriate.
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